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SEMI M66 Document Information:
Title
TEST METHOD TO EXTRACT EFFECTIVE WORK FUNCTION IN OXIDE AND HIGH-? GATE STACKS USING THE MIS FLAT BAND VOLTAGE-INSULATOR THICKNESS TECHNIQUE
Semiconductor Equipment and Materials International
Publication Date:
Jul 1, 2006
Scope:
This test method covers determination of the effective work
function of both oxide and high-k gate stacks. While the basic
technique is based upon the conventional MOS capacitor flat band
voltage-dielectric thickness approach as outlined in SEMI MF1153,
two features of the present test method are keys to its usefulness:
(1) the ability to provide a demonstrably good estimate of
effective work function from measurements on a single silicon
wafer, and (2) the ability to separate and minimize the effects of
interfacial and bulk charge distributions in a high-k gate stack on
the effective work function value. Both of these features depend
upon the nature and fabrication of the test structures used for the
test method. The nature of the samples is so important to the
application of the method that the terraced oxide technique, an
automated approach to fabrication of suitable test structures using
standard tools available in modern wafer fabs, is outlined as part
of the test method and alternative, but probably less accurate and
less reproducible, approaches suitable for use in smaller
facilities are outlined in Related Information 1.
The use of a single silicon wafer that includes a range of
dielectric thicknesses is the first key feature of this test
method. This requirement was a standard feature of early
measurements of effective work function by this technique, based on
the convenience of etching a thermally grown oxide manually, by
dipping it partially into a wet etchant. This approach maintains
the validity of the procedure by assuring a uniform oxide-silicon
interface charge density, for all test specimens included in the
evaluation.
Equation 1 establishes that all the capacitors with varying
oxide thickness must have the same value of Qf
to evaluate the gate electrode-silicon work function difference
F'ms by plotting the flat band voltage
Vfb against the varying oxide thickness
Wox. F'ms is used with the
known work function of the silicon substrate to obtain the desired
effective work function of the gate electrode material under
investigation. Difficulty in building wafers in a modern wafer fab
by varying the oxide thickness in a controlled fashion has led to
the use of different wafers with fixed thicknesses for these
experiments. Such samples may well have differing values of
Qf because of differing oxidation temperatures,
ambients, or times. This is even more likely to be the case for
high-k gate stacks, with their differing deposition conditions.
Thus, this test method stresses the use of single wafers with
varying oxide thicknesses for extracting effective work
function.
This test method specifically covers the extraction of effective
work function for gate electrodes on high-k gate stacks. The
interaction of certain electrodes with high-k dielectric surfaces
can cause work functions to vary, depending upon the surface upon
which the electrode is placed. The analysis can be simplified
considerably by using high-k gate stack structures in which a fixed
thickness of the high-k film is placed over the varying oxide
thickness on a single wafer. In this case, charge distributions
associated with the high-k film and its interface with the oxide
will affect the ordinate intercept of the Vfb –
Wox plot, interfering with the determination of
F'ms. This interference can often be reduced to
negligible levels by using thin high-k films. Where necessary, the
magnitude of the fixed shift in the ordinate intercept can be
evaluated by using multiple wafers with varying high-k film
thicknesses (see Related Information 2).
This test method requires the measurement of many MIS
capacitance-voltage (C-V) curves, and extraction of the flat band
voltage and equivalent oxide thickness (EOT) from this data. These
C-V curves are high frequency C-V curves, typically measured at
frequencies ranging from 100 kHz to 1 MHz. Accurate measurements of
such C-V curves, particularly on relatively thin oxides or high-k
gate stacks, have many potential complications, the description of
which is not included in SEMI MF1153, which covers measurements on
oxides = 50 nm thick, and is also beyond the scope of this test
method.2,3
Extraction of values of Vfb and EOT from the
C-V data taken here is an important part of the procedure. In the
work shown herein, the CVC algorithm3 developed by NCSU
has been used. This is not critical to the analysis. Any consistent
algorithm for this purpose may be used with the data.
NOTICE: This standard does not purport to
address safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish
appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
Purpose
Continued scaling of CMOS integrated circuit dimensions is
reaching a point where materials changes as well as lithographic
advances are required to meet the projections of Moore's Law and
the International Technology Roadmap for Semiconductors.
As gate dielectric thickness approaches 1 nm, both the gate
dielectric and electrode materials that have been in common
usage—SiO2, and doped polysilicon—are displaying
characteristics that are unacceptable for upcoming technology
nodes. Research to find suitable replacements for the
n+ and p+ polysilicon gate
electrodes used in conventional CMOS is placing renewed emphasis on
experimental determination of the effective gate electrode work
function of candidate materials.
One aspect of the research for new gate electrode materials is
that they may be required for use on either silicon dioxide
(SiO2) gate dielectrics or on the high-k gate
dielectrics that are being developed to replace SiO2.
While it might seem that gate electrode work function differences
should depend only upon the properties of the gate electrode
material and the silicon substrate, it has been shown that various
metal-dielectric interactions may cause potential shifts that
affect the effective work function. Thus consideration must be
given to structures and analyses that properly take these effects
into account.
Changes in process technology and wafer fabrication practice
since these measurements were first widely used suggest a need for
revised approaches to test structure fabrication and analysis.
Definition of such changes is the purpose of this test method,
which covers the measurement, analysis and reporting of effective
gate electrode work function data by the flat band
voltage-insulator thickness technique.
2 High frequency MOS C-V measurement theory and techniques are
described in Schroder, D. K. Semiconductor Material and Device
Characterization (John Wiley & Sons, Inc., New York, 1990)
Chapter 6, p. 244ff, and Nicollian, E. H. and Brews, J.
R., (MOS (Metal Oxide Semiconductor) Physics and
Technology (John Wiley & Sons, Inc., New York, 1982)
Chapter 4, p. 99ff and Chapter 12, p. 581ff.
3 Hauser, J. R. and Ahmed, K., "Characterization of Ultra-Thin
Oxides Using Electrical C-V and I-V Measurements," in
Characterization and Metrology for ULSI Technology,
Seiler, D.G., et al. ed., AIP Conference Proceedings 449
(American Institute of Physics, Woodbury, NY, 1998) pp.
235–239.
Keywords:
- barrier height
- effective work function
- equivalent oxide thickness
- flat band voltage
- gate electrode
- work function
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