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SEMI M60 Document Information:
Title
TEST METHOD FOR TIME DEPENDENT DIELECTRIC BREAKDOWN CHARACTERISTICS OF SiO2 FILMS FOR Si WAFER EVALUATION
Semiconductor Equipment and Materials International
Publication Date:
Mar 1, 2006
Scope:
This test method is for the purpose of the characterization
method of silicon wafer by GOI. This characterization method is
outlined below
MOS (Metal Oxide Semiconductor) — capacitor
fabrication — A gate oxide film is thermally grown on a
silicon wafer surface. Then, poly-Si electrodes are formed on the
gate oxide film. Other metals, other than poly-silicon electrode
materials, can be used, however, it shall be desirable to use an
electrode that has been confirmed to have sufficiently good
characteristics for application as a gate electrode as described
below.
Electrical Characterization Evaluation — The TDDB (Time
Dependent Dielectric Breakdown) characteristics of the MOS
capacitors are measured. The presence of COPs (Crystal Originated
Particles) at the surface of the polished Si substrates influences
the TDDB characteristics of the gate oxide. That is, the silicon
wafer is evaluated in terms of the TDDB characteristics of the gate
oxide. The test method outlined in this test method is for the
purpose of standardizing the procedure of MOS fabrication,
measurement, analyses, and the report of the GOI data to interested
parties. This test method is based on the results of round robin
among the silicon wafer manufacturers. In general, GOI strongly
depends on crystal defects, contaminations and particles on/near
wafer surface. GOI also depends on the fabrication environment. The
cleanliness of the process environment in which the MOS capacitors
are fabricated shall be evaluated to be acceptable (see ¶ 5.3).
The target of this test method is to characterize silicon
wafers, that is, evaluate COPs near the silicon wafer surface. The
proper gate oxide thickness of the MOS samples is 20–25 nm. A
discussion on gate oxide thickness is given in a later section.
Oxygen precipitates are also one of the gate oxide defect origins,
however, this is beyond the scope of this test method because the
as-received wafers contain only a small amount of oxygen
precipitates. Near-surface quality can be evaluated in this test.
In this case, it is assumed that an oxide film thickness of
approximately 10 nm is used. It is more difficult to categorize the
accidental and intrinsic breakdowns in TZDB, as the gate oxide
thickness becomes thinner. Therefore mode classification in TDDB is
more effective.
For detailed discussion on sample structures used in this test
method, the reader shall refer to EIA/JEDEC Standard 35-1. In
general, the most likely sample structures are a simple planar MOS
(Metal Oxide Semiconductor) capacitor structure, various isolation
structures (for example, LOCOS (LOCal Oxidation of Silicon), STI
(Shallow Trench Isolation)), and FET (Field-Effect Transistor)
structures. For the purpose of silicon wafer characterization, the
simple planar MOS capacitor structure is the most desirable. In the
case of the various isolation and FET structures, the silicon wafer
receives thermal treatments several times in the complicated sample
fabrication process. Therefore, in this case it is questionable
whether the characteristics of the starting Si wafer are reflected
in this test measurement results.
In this evaluation method, a constant current stress is applied
to the gate oxide and time to breakdown is measured. The amount of
charge injected until dielectric breakdown (Qbd) is also
calculated. (Constant-current TDDB: detail of measurement condition
is described in a later section). The dielectric breakdown by the
COPs and other defects can be evaluated from the accumulated
failure distribution of Qbd. In addition, a
constant-voltage TDDB method can be used as an evaluation of gate
oxide lifetime. In this test method, the constant-current TDDB
method is chosen, because the constant current TDDB method has less
influence on parasitic resistance in a measurement circuit than the
constant-voltage TDDB method.
This test method gives instructions for the procedure for
characterizing mirror-polished, p-type CZ silicon wafers. Gate
electrodes were negatively biased so that the silicon surface is in
accumulation. Stress current shall be sufficient for the gate oxide
to be broken down within a finite measurement time. In addition, it
is desirable to have an applied current density J within 0.001 and
0.1A/cm2.
The stress gate current has to be reversed for the n-type
silicon wafer.
The poly-silicon film is used as gate electrode of measured MOS
capacitors. The poly-silicon film can make standard test results
applicable to the testing of wafers used to fabricate integrated
circuits rather than other metal electrodes because poly-silicon
electrodes are commonly used in actual devices. However, a gate
electrode other than poly-silicon gate electrode shall be studied
for applications in advanced ultralarge-scale integrated circuits.
In this case, the new electrode material shall have the same
detection sensitivity to silicon wafer defects as poly-silicon
electrode.
NOTICE: This test method does not purport to
address safety issues, if any, associated with its use. It is the
responsibility of the users of this test method to establish
appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
Purpose
The technique outlined in this test method is for the purpose of
standardizing silicon wafer characterization by GOI (Gate Oxide
Integrity). For more detailed discussion of the general
characterizing methods for this test, the reader is referred to §
3. TZDB technique as SEMI M51 is advantageous to estimate failure
rate by intrinsic breakdown as the C mode and an accidental
breakdown as the B mode. However, this test method has a higher
sensitivity for detecting the accidental breakdown mode than
TZDB.
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