IEEE 1164 ERTA Standard Multivalue Logic System for VHDL Model Interoperability (Std_Logic_1164)

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IEEE 1164 ERTA Document Information:

Title
Standard Multivalue Logic System for VHDL Model Interoperability (Std_Logic_1164)

The Institute of Electrical and Electronics Engineers, Inc.

Publication Date:
Sep 27, 1995

Scope:

This standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 package body along with this clause 1 documentation. The information annex A is a guide to users and is not part of this standard, but suggests ways in which one might use this package.

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