SEMI M71 SPECIFICATION FOR SILICON-ON-INSULATOR (SOI) WAFERS FOR CMOS LSI 130 nm TECHNOLOGY GENERATION AND BEYOND

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SEMI M71 Document Information:

Title
SPECIFICATION FOR SILICON-ON-INSULATOR (SOI) WAFERS FOR CMOS LSI 130 nm TECHNOLOGY GENERATION AND BEYOND

Semiconductor Equipment and Materials International

Publication Date:
Nov 1, 2007

Scope:

This specification defines the properties of SOI wafers that are meant for use in LSI CMOS applications. It specifies the general characteristics of 200 mm and 300 mm notched SOI wafers and it facilitates selection of customer-driven parameters for ultra-thin SOI (Si film 20–50 nm). It also includes specifications for 200 and 300 mm diameter SOI wafers that have somewhat thicker Si films (50 nm < Si < 200 nm) that are currently covered in SEMI M47. This specification is intended to be used with the polished wafer specification [SEMI M1]. In the case when epitaxial layers are used in fabrication of SOI wafers, the epitaxial wafer specification [SEMI M62], which defines the properties of the epitaxial layer, should also be utilized.

NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.

Purpose

This specification defines thin-layer silicon-on-insulator (SOI) wafer requirements for CMOS large-scale integrated circuit (LSI) devices for the 130nm technology node and beyond (65 nm, 45 nm, etc). By defining parameters, inspection procedures and acceptance criteria, both suppliers and customers may uniformly define product characteristics and quality requirement.

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