SEMI M17 GUIDE FOR A UNIVERSAL WAFER GRID

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SEMI M17 Document Information:

Title
GUIDE FOR A UNIVERSAL WAFER GRID

Semiconductor Equipment and Materials International

Publication Date:
Jul 1, 2004

Scope:

This document defines a grid pattern that is useful for quantifying surface defects on a nominally circular semiconductor wafer. The grid is defined such that it contains 1000 elements of approximately equal area. Each grid element thus contains 0.1 percent of the total quality area of the surface being inspected. Defects that are non-uniformly distributed (for example, slip) can be quantified in terms of the percent defective (or percent useful) area on the wafer surface.

The grid described is referenced to the center of the wafer. A concept of a "Fixed Quality Area" is used, based on nominal wafer diameter, such as is specified in SEMI M1.

Methods for observing these defects on silicon wafer surfaces are outside the scope of this guide. Such methods may be found in SEMI MF1725, SEMI MF1726, JIS H 0609, and DIN 50434.

NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the users of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.

Purpose

Maximum allowable slip and other non-uniformly distributed defects are frequently specified when procuring polished and epitaxial silicon wafers. SEMI M2 specifies a maximum allowable fraction of the epitaxial wafer surface area that can contain slip.

This guide provides a design for and guidance for use of a wafer grid that facilitates the determination of the fraction of the wafer surface area covered by observed defects.

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