IEEE Begins Standard for Esterel Reference Manual - IEEE P1778
April 20, 2007 // Published as a news service by IHS
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The Institute of Electrical and Electronics Engineers (IEEE) began work on IEEE P1778 - Standard for Esterel version 7 (v7) Language Reference Manual, a standard that will stabilize and fully define the syntax and semantics of this language.
Esterel v7 expresses the interaction of hardware, software and temporal synchronization and helps increase design efficiency and reliability for semiconductor and other embedded systems. It is scheduled for completion in mid 2008.
Esterel v7 designs are typically three to five times smaller than those based on hardware description languages (HDL) or C software and so are usually easier to develop, verify and communicate, said the IEEE.
This language is interoperable with other standards because it generates both synthesizable HDL code, such as Verilog and VHSIC Hardware Description Language (VHDL), and executable software code in C, C++, SystemC and other packages.
Since it offers equivalent hardware and software targets from a single source, it is designed to build confidence in computer-based hardware simulation and speeds decision making in hardware and software implementation.
"IEEE P1778 will give the electronic design automation, semiconductor, systems design and software communities a standard Esterel v7 language," said Gérard Berry, chair of the Esterel v7 Language Reference Working Group and chief scientist of Esterel Technologies.
"This reference manual will ensure the full interoperability among Esterel-based compilation, circuit synthesis, static analysis and verification tools."
Esterel v7 gives users a higher level of abstraction than do other languages by integrating such areas as the sequencing found in software languages, large-scale hardware description languages and support for multiclock designs. It can be translated to hardware circuit descriptions written in standard HDLs or to equivalent software code.
The Esterel Consortium developed the Esterel v7 language by adding hardware design features to Esterel v5, a version formulated in academia. IEEE P1778 is part of the IEEE's broad electronic design automation activities effort that include seven VHDL standards, three Verilog HDL standards, the SystemC language reference manual and standards for the Property Specification Language and the Functional Verification Language 'e'.
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IEEE P1778 is sponsored by the IEEE Computer Society, Design Automation Standards Committee.
Source: Institute of Electrical and Electronics Engineers (IEEE).